PIC18F26J50-I/SS

Key features

• Deep Sleep mode: CPU off, Peripherals off, Currents Down to 13 nA and 850 nA with RTCC: Able to wake-up on external triggers, programmable WDT or RTCC alarm, Ultra Low-Power Wake-up (ULPWU)
• Sleep mode: CPU off, Peripherals off, SRAM on, Fast Wake-up, Currents Down to 105 nA, Typical
• Idle: CPU off, Peripherals on, Currents Down to 2.3 μA, Typical
• Run: CPU on, Peripherals on, Currents Down to 6.2 μA, Typical
• Timer1 Oscillator w/RTCC: 1 μA, 32 kHz, Typical
• Watchdog Timer: 0.8 μA, 2V, Typical
• Low-Power, High-Speed CMOS Flash Technology
• C Compiler Optimized Architecture for Re-Entrant Code
• Priority Levels for Interrupts
• Self-Programmable under Software Control
• 8x8 Single-Cycle Hardware Multiplier
• Extended Watchdog Timer (WDT): Programmable period from 4 ms to 131s
• Single-Supply In-Circuit Serial Programming (ICSP) via two pins
• In-Circuit Debug (ICD) w/Three Breakpoints via 2 Pins
• Operating Voltage Range of 2.0V to 3.6V
• On-Chip 2.5V Regulator
• Flash Program Memory of 10,000 Erase/Write Cycles Minimum and 20-Year Data Retention
• USB V2.0 Compliant
• Full Speed (12 Mbps) and Low Speed (1.5 Mbps)
• Supports Control, Interrupt, Isochronous and Bulk Transfers
• Supports up to 32 Endpoints (16 bidirectional)
• USB module can use any RAM Location on the Device as USB Endpoint Buffers
• On-Chip USB Transceiver with Crystal-less operat