PIC24FJ128GC006-I/PT

Key features

• 12 - Bit, up to 50 - Channel, High - Speed, Pipeline Analog - to - Digital Converter (A/D):
• Conversion rates up to 10 Msps
• Compatibility features for low conversion rates
• Flexible operating modes with auto - accumulate, threshold Defect and channel scan using sample lists
• Conversion available during Sleep and Idle
• 16 - Bit Sigma - Delta Analog - to - Digital Converter (A/D):
• Programmable data rate with dithering option and adjustable oversampling ratios
• Two differential channels
• Configurable input gain stage
• Two 10 - Bit Digital - to - Analog Converters (DAC):
• Fast settling time supports 1 Msps update rate
• Two Rail - to - Rail Input/Output, General Purpose Operational Amplifiers:
• 2.5 MHz gain bandwidth product (typical)
• Flexible input multiplexing options
• Optional Comparator mode
• Three Rail - to - Rail, Enhanced Analog Comparators with Programmable Input/Output Configuration
• Three On - Chip Programmable Voltage References
• Charge Time Measurement Unit (CTMU):
• Used for capacitive touch sensing, up to 50 channels
• Time measurement down to 100 ps resolution
• Operation in Sleep mode
• Multiple Power Management Options for Extreme Power Reduction:
• VBAT allows for lowest power consumption on backup battery (with or without RTCC)
• Deep Sleep allows near total power - down, with the ability to wake - up on internal or external triggers
• Full RAM and state retention in select Deep Sleep and VBAT modes
• Sleep and Idle modes selectively shut down peripherals and/or core for substantial power reduction and fast wake - up
• Doze mode allows CPU to run at a lower clock speed than peripherals
• Alternate Clock modes allow On - the - Fly Switching to a Lower Clock Speed for Selective Power Reduction
• Extreme Low - Power Current Consumption for Deep Sleep:
• WDT: 270 nA @ 3.3V, typical
• RTCC: 350 nA @ 32 kHz, 3.3V, typical
• Deep Sleep current, 75 nA, 3.3V, typical
• USB v2.0 On - The - Go (OTG) Compliant
• USB Device mode Operation from FRC Oscillator - No Crystal Oscillator Required
• Dual Role Capable - Can Act as Either Host or Peripheral
• Low - Speed (1.5 Mb/s) and Full - Speed (12 Mb/s) USB Operation in Host mode
• Full - Speed USB Operation in Device mode
• Low Jitter PLL for USB
• Supports up to 32 Endpoints (16 bidirectional):
• USB module can use any RAM location on the device as USB endpoint buffers
• On - Chip USB Transceiver with Interface for Off - Chip USB Transceiver
• Supports Control, Interrupt, Isochronous and Bulk Transfers
• On - Chip Pull - up and Pull - Down Resistors
• LCD Display Controller:
• Up to 59 segments by 8 commons
• Internal charge pump and low - power, internal resistor biasing
• Operation in Sleep mode
• Up to Five External Interrupt Sources
• Peripheral Pin Select (PPS); Allows Independent I/O Mapping of Many Peripherals
• Five 16 - Bit Timers/Counters with Prescaler:
• Can be paired as 32 - bit timers/counters
• Six - Channel DMA Supports All Peripheral modules:
• Minimizes CPU overhead, increases data throughput and lowers power consumption
• Nine Input Capture modules, each with a Dedicated 16 - Bit Timer
• Nine Output Compare/PWM modules, each with a Dedicated 16 - Bit Timer
• Enhanced Parallel Master/Slave Port (EPMP/EPSP)
• Hardware Real - Time Clock and Calendar (RTCC):
• Run, Sleep, Deep Sleep and VBAT modes
• Two 3 - Wire/4 - Wire SPI modules (support 4 Frame modes) with 8 - Level FIFO Buffer
• Two I²C modules Support Multi - Master/Slave mode and 7 - Bit/10 - Bit Addressing
• Four UART modules:
• Support RS - 485, RS - 232 and LIN/J2602
• On - chip hardware encoder/decoder for IrDA
• Auto - wake - up on Auto - Baud Detect (ABD)
• 4 - level deep FIFO buffer
• Programmable, 32 - Bit Cyclic Redundancy Check (CRC) Generator
• Digital Signal Modulator (DSM) Provides On - Chip FSK and PSK Modulation for a Digital Signal Stream
• High - Current Sink/Source (18 mA/18 mA) on All I/O Pins
• Configurable Open - Drain Outputs on Digital I/O Pins
• 5.5V Tolerant Inputs on Select Pins
• Modified Harvard Architecture
• Up to 16 MIPS Operation @ 32 MHz
• C Compiler Optimized Instruction