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PIC24FJ64GA106-I/PT MICROCHIP
MICROCHIP

PIC24FJ64GA106-I/PT

PIC 16 Bit 32MHz TQFP-64(10x10) Microcontrollers RoHS

TQFP-64(10x10)ROHS3 CompliantActive

64/80/100-Pin, 16-Bit, General Purpose Flash Microcontrollers with Peripheral Pin Select (PPS)

Manufacturer
MICROCHIP
Manufacturer part #
PIC24FJ64GA106-I/PT
Store part #
C634748
Package / case
TQFP-64(10x10)
Packaging
Tray
Datasheet (PDF)

Every Order Guarantee

100% Authentic · 30-Day Return or Replacement · policy

4 in stock

#C634748

Stock & price checked 3 days ago

QuantityUnit pricePack price
1+₹1,124.60₹1,124.60
10+₹1,098.88₹10,988.80
30+₹1,081.88₹32,456.40
100+₹1,064.67₹1,06,467.00

1 × ₹1,124.60

₹1,124.60

excl. GST

₹1,327.03 incl. 18% GST

Need volume or a scheduled delivery? Request a quote
  • Dispatch in 15-18 working days
  • GST invoice with every order
  • Standard pack: 160 per tray

PIC24FJ64GA106-I/PT

₹1,124.60 for 1 + GST

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Specifications

ADC (Bit)
10bit
Number of I/O
53
Operating Temperature
-40℃~+85℃
Voltage - Supply
2V~3.6V
Program Memory Type
FLASH
Program Storage Size
64KB
CPU Core
PIC
Core Size
16 Bit
CPU Maximum Speed
32MHz
Oscillator Type
Built-in

Packaging & compliance

RoHS
ROHS3 Compliant
Lifecycle
Active
ECCN
3A991A2
Packaging
Tray
Standard pack
160 / Tray
Sold per
Piece
Minimum order
1
Unit weight
0.37 g

Overview

Key features

  • On-Chip 2.5V Voltage Regulator
  • Switch between Clock Sources in Real Time
  • Idle, Sleep and Doze modes with Fast Wake-up and Two-Speed Start-up
  • Run mode: 1 mA/MIPS, 2.0V Typical
  • Standby Current with 32 kHz Oscillator: 2.6 μA, 2.0V Typical
  • Modified Harvard Architecture
  • Up to 16 MIPS Operation at 32 MHz
  • 8 MHz Internal Oscillator
  • 17-Bit x 17-Bit Single-Cycle Hardware Multiplier
  • 32-Bit by 16-Bit Hardware Divider
  • 16 x 16-Bit Working Register Array
  • C Compiler Optimized Instruction Set Architecture with Flexible Addressing modes
  • Linear Program Memory Addressing, Up to 12 Mbytes
  • Linear Data Memory Addressing, Up to 64 Kbytes
  • Two Address Generation Units (AGUs) for Separate Read and Write Addressing of Data Memory
  • 10-Bit, Up to 16-Channel Analog-to-Digital (A/D) Converter at 500 ksps: Conversions available in Sleep mode
  • Three Analog Comparators with Programmable Input/ Output Configuration
  • Charge Time Measurement Unit (CTMU)
  • Peripheral Pin Select: Allows independent I/O mapping of many peripherals at run time; Continuous hardware integrity checking and safety interlocks prevent unintentional configuration changes; Up to 46 available pins (100-pin devices)
  • Three 3-Wire/4-Wire SPI modules (support 4 Frame modes) with 8-Level FIFO Buffer
  • Three I²C modules support Multi-Master/Slave modes and 7-Bit/10-Bit Addressing
  • Four UART modules: Supports RS-485, RS-232, LIN/J2602 protocols and IrDA; On-chip hardware encoder/decoder for IrDA; Auto-wake-up and Auto-Baud Detect (ABD); 4-level deep FIFO buffer
  • Five 16-Bit Timers/Counters with Programmable Prescaler
  • Nine 16-Bit Capture Inputs, each with a Dedicated Time Base
  • Nine 16-Bit Compare/PWM Outputs, each with a Dedicated Time Base
  • 8-Bit Parallel Master Port (PMP/PSP): Up to 16 address pins; Programmable polarity on control lines
  • Hardware Real-Time Clock/Calendar (RTCC): Provides clock, calendar and alarm functions
  • Programmable Cyclic Redundancy Check (CRC) Generator
  • Up to Five External Interrupt Sources
  • Operating Voltage Range of 2.0V to 3.6V
  • Self-Reprogrammable under Software Control
  • 5.5V Tolerant Input (digital pins only)
  • Configurable Open-Drain Outputs on Digital I/Os
  • High-Current Sink/Source (18 mA/18 mA) on all I/Os
  • Selectable Power Management modes: Sleep, Idle and Doze modes with fast wake-up
  • Fail-Safe Clock Monitor Operation: Detects clock failure and switches to on-chip FRC oscillator
  • On-Chip LDO Regulator
  • Power-on Reset (POR), Power-up Timer (PWRT), Low-Voltage Detect (LVD) and Oscillator Start-up Timer (OST)
  • Flexible Watchdog Timer (WDT) with On-Chip Low-Power RC Oscillator for Reliable Operation
  • In-Circuit Serial Programming (ICSP) and In-Circuit Debug (ICD) via Two Pins
  • JTAG Boundary Scan Support
  • Brown-out Reset (BOR)
  • Flash Program Memory: 10,000 erase/write cycle endurance (minimum); 20-year data retention minimum; Selectable write protection boundary; Write protection option for Flash Configuration Words

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