PIC24FJ64GA306T-I/PT

Key features

• Multiple Power Management Options for Extreme Power Reduction:
• VBAT allows the device to transition to a backup battery for the lowest power consumption with RTCC
• Deep Sleep allows near total power-down with the ability to wake-up on external triggers
• Sleep and Idle modes selectively shut down peripherals and/or core for substantial power reduction and fast wake-up
• Doze mode allows CPU to run at a lower clock speed than peripherals
• Alternate Clock modes Allow On-the-Fly Switching to a Lower Clock Speed for Selective Power Reduction
• Extreme Low-Power Current Consumption for Deep Sleep:
• WDT: 270 nA @3.3V typical
• RTCC: 400 nA @ ≈32 kHz, 3.3V typical
• Deep Sleep current, 40 nA, 3.3V typical
• LCD Display Controller:
• Up to 60 segments by 8 commons
• Internal charge pump and low-power, internal resistor biasing
• Operation in Sleep mode
• Up to Five External Interrupt Sources
• Peripheral Pin Select (PPS): Allows Independent I/O Mapping of Many Peripherals
• Five 16-Bit Timers/Counters with Prescaler:
• Can be paired as 32-bit timers/counters
• Six-Channel DMA supports All Peripheral modules:
• Minimizes CPU overhead and increases data throughput
• Seven Input Capture modules, each with a Dedicated 16-Bit Timer
• Seven Output Compare/PWM modules, each with a Dedicated 16-Bit Timer
• Enhanced Parallel Master/Slave Port (EPMP/EPSP)
• Hardware Real-Time Clock/Calendar (RTCC):
• Runs in Deep Sleep and VBAT modes
• Two 3-Wire/4-Wire SPI modules (support 4 Frame modes) with 8-Level FIFO Buffer
• Two I²C modules Support Multi-Master/Slave mode and 7-Bit/10-Bit Addressing
• Four UART modules:
• Support RS-485, RS-232 and LIN/J2602
• On-chip hardware encoder/decoder for IrDA
• Auto-wake-up on Auto-Baud Detect
• 4-level deep FIFO buffer
• Programmable 32-Bit Cyclic Redundancy Check (CRC) Generator
• Digital Signal Modulator Provides On-Chip FSK and PSK Modulation for a Digital Signal Stream
• Configurable Open-Drain Outputs on Digital I/O Pins
• High-Current Sink/Source (18 mA/18 mA) on All I/O Pins
• 10/12-Bit, 24-Channel Analog-to-Digital (A/D) Converter:
• Conversion rate of 500 ksps (10-bit), 200 ksps (12-bit)
• Conversion available during Sleep and Idle
• Three Rail-to-Rail Enhanced Analog Comparators with Programmable Input/Output Configuration
• On-Chip Programmable Voltage Reference
• Charge Time Measurement Unit (CTMU):
• Used for capacitive touch sensing, up to 24 channels
• Time measurement down to 1 ns resolution
• CTMU temperature sensing
• Modified Harvard Architecture
• Up to 16 MIPS Operation @32 MHz
• 8 MHz Internal Oscillator:
• 4x PLL option
• Multiple clock divide options
• Fast start-up
• 17-Bit x 17-Bit Single-Cycle Hardware Fractional/Integer Multiplier
• 32-Bit by 16-Bit Hardware Divider
• 16x16-Bit Working Register Array
• C Compiler Optimized Instruction Set Architecture
• Two Address Generation Units for Separate Read and Write Addressing of Data Memory
• Operating Voltage Range of 2.0V to 3.6V
• Two On-Chip Voltage Regulators (1.8V and 1.2V) for Regular and Extreme Low-Power Operation
• 20,000 Erase/Write Cycle Endurance Flash Program Memory, Typical
• Flash Data Retention: 20 Years Minimum
• Self-Programmable under Software Control
• Programmable Reference Clock Output
• In-Circuit Serial Programming (ICSP) and In-Circuit Emulation (ICE) via 2 Pins
• JTAG Boundary Scan Support
• Fail-Safe Clock Monitor Operation:
• Detects clock failure and switches to on-chip, low-power RC oscillator
• Power-on Reset (POR), Power-up Timer (PWRT) and Oscillator Start-up Timer (OST)
• Brown-out Reset (BOR) with Operation Below VBOR
• High/Low-Voltage Detect (HLVD)
• Flexible Watchdog Timer (WDT) with its Own RC Oscillator for Reliable Operation
• Standard and Ultra Low-Power Watchdog Timers (ULPW) for Reliable Operation in Standard and Deep Sleep modes