PIC32MX564F064H-I/PT

Key features

• MIPS16e® mode for up to 40% smaller code size
• Code-efficient (C and Assembly) architecture
• Single-cycle (MAC) 32x16 and two-cycle 32x32 multiply
• 0.9% internal oscillator (on some variants)
• Programmable PLLs and oscillator clock sources
• Fail-Safe Clock Monitor (FSCM)
• Independent Watchdog Timer
• Fast wake-up and start-up
• Low-power management modes (Sleep and Idle)
• Integrated Power-on Reset, Brown-out Reset
• 0.5 mA/MHz dynamic current (typical)
• 41 μA IPD current (typical)
• External graphics interface with up to 34 Parallel Master Port (PMP) pins: Interface to external graphics controller; Capable of driving LCD directly with DMA and internal or external memory
• ADC Module: 10-bit 1 Msps rate with one Sample and Hold (S&H); 16 analog inputs; Can operate during Sleep mode
• Flexible and independent ADC trigger sources
• Comparators: Two dual-input Comparator modules; Programmable references with 32 voltage points
• Five General Purpose Timers: Five 16-bit and up to two 32-bit Timers/Counters
• Five Output Compare (OC) modules
• Five Input Capture (IC) modules
• Real-Time Clock and Calendar (RTCC) module
• USB 2.0-compliant Full-Speed OTG controller
• 10/100 Mbps Ethernet MAC with MII and RMII interface
• CAN module: 2.0B Active with DeviceNet addressing support
• Six UART modules (20 Mbps): Supports LIN 2.1 protocols and IrDA support
• Up to four 4-wire SPI modules (25 Mbps)
• Up to five I²C modules (up to 1 Mbaud) with SMBus support
• Parallel Master Port (PMP)
• Up to eight channels of hardware DMA with automatic data size detection
• 32-bit Programmable Cyclic Redundancy Check (CRC)
• Six additional channels dedicated to USB, Ethernet and CAN modules
• 15 mA or 10 mA source/sink for standard VOH/VOL and up to 22 mA for non-standard VOH1
• 5V-tolerant pins
• Selectable open drain and pull-ups
• External interrupts
• Class B Safety Library, IEC 60730
• In-circuit and in-application programming
• 4-wire MIPS® Enhanced JTAG interface
• Unlimited program and six complex data breakpoints
• IEEE 1149.2-compatible (JTAG) boundary scan