R7F100GLG2DFB#AA0

True low-power platform, 41 - μA/μHz operating current, 210-nA data retention current for 4 KB of RAM, up to 768-KB code flash memory and 48-KB RAM, capacitive sensing unit, from 30 to 128 pins, 1.6 - 5.5 V

Key features

• Ultra-low power consumption technology
• VDD: single power supply voltage of 1.6 to 5.5 V
• HALT mode
• STOP mode
• High-speed wakeup from the STOP mode is possible.
• SNOOZE mode
• RL78 CPU core: CISC architecture with 3-stage pipeline
• Minimum instruction execution time: Can be changed from high speed (0.03125 μs @ 32 MHz operation with the high - speed on - chip oscillator clock) to ultra - low speed (30.5 μs @ 32.768 kHz operation with the subsystem clock)
• Multiply/divide/multiply & accumulate instructions are supported.
• Address space: 1 MB
• General - purpose registers: (8 - bit register × 8) × 4 banks
• On - chip RAM: 12 to 48 KB
• Code flash memory: 96 to 768 KB
• Block size: 2 KB
• Prohibition of block erase and rewriting (security function)
• On - chip debugging
• Self - programming (with boot swapping and flash shield window)
• Data flash memory: 8 KB
• Background operation (BGO): Instructions can be executed from the program memory while rewriting the data flash memory.
• Number of rewrites: 1,000,000 times (typ.)
• High - speed on - chip oscillator: Select from 32 MHz, 24 MHz, 16 MHz, 12 MHz, 8 MHz, 6 MHz, 4 MHz, 3 MHz, 2 MHz, or 1 MHz
• High accuracy: ±1.0% (VDD = 1.8 to 5.5 V, TA = - 20 to + 85 ℃)
• Middle - speed on - chip oscillator: Select from 4 MHz, 2 MHz, or 1 MHz (with adjustability)
• Low - speed on - chip oscillator: 32.768 kHz (typ.) (with adjustability)
• Operating ambient temperature: TA = - 40 to + 85 ℃ (2D: Consumer applications); TA = - 40 to + 105 ℃ (3C: Industrial applications)
• Power management and reset function: On - chip power - on - reset (POR) circuit; On - chip voltage detectors (LVD0 and LVD1)
• Data transfer controller (DTC): Transfer modes: Normal transfer mode, repeat transfer mode, block transfer mode; Activation sources: Activated by interrupt sources; Chain transfer function
• SNOOZE mode sequencer (SMS): Calculations and comparison of values by the commands for use in processing by the sequencer can realize intermittent operations where the RL78/G23 does not have to return to normal operation.
• Sequentially handling a total of 32 processes with the use of desired commands from among 21 different ones
• The SNOOZE mode sequencer offers operation with low power consumption without using the CPU, flash memory, and RAM.
• Logic and event link controller (ELCL): Event signals can be set up between specified peripheral functions.
• The signals can be generated by the input of multiple event signals to the logic circuit.
• Flip - flop circuits are incorporated to handle setting and resetting functions.
• Serial interface: Simplified SPI (CSINote 1): 3 to 8 channels; UART/UART (LIN - bus supported)/UARTA: 3 to 6 channels; I2C/Simplified I2C: 4 to 10 channels
• Remote control signal receiver: 1 channel; Matching of 4 waveform patterns (header, data 0, data 1, and special data)
• Timers: 16 - bit timer: 8 to 16 channels; 32 - bit interval timer: 1 channel in 32 - bit counter mode, 2 channels in 16 - bit counter mode, 4 channels in 8 - bit counter mode; Realtime clock: 1 channel (counting of one second to 99 years, alarm interrupt, and clock correction); Watchdog timer: 1 channel (operates with the dedicated low - speed on - chip oscillator clock)
• A/D converter: 8 -/10 -/12 - bit resolution A/D converter; Analog input: 8 to 26 channels; Internal reference voltage (1.48 V) and temperature sensor
• D/A converter: 8 - bit resolution D/A converter; Analog output: 2 channels; Output voltage: 0 V to VDD; Realtime output function
• Comparator: 2 channels; Operating modes: Comparator high - speed mode and comparator low - speed mode; The external reference voltage and the internal reference voltage or D/A converter output are selectable as the reference voltage.
• Capacitive sensing unit: CTSU2L operating voltage condition: VDD = 1.8 to 5.5 V; Self - capacitance method: A single pin configures a single key, supporting up to 32 keys; Mutual capacitance method: Matrix configuration with 8 × 8 pins, supporting up to 64 keys
• Input/output port pins: Number of port pins: 26 to 120 (N - ch open drain I/O [withstand voltage of 6 V]: 2 to 4, N - ch open drain I/O [VDD withstand voltageNote 2/EVDD withstand voltageNote 3]: 10 to 33, output current control pins: 6 to 8); Can be set to N - ch open drain or TTL input buffer, and use of an on - chip pull - up resistor can be specified.
• Connectable to a device with different voltage (1.8, 2.5, or 3 V)
• Others: Key interrupt input; Clock output/buzzer output controller; BCD (binary - coded decimal) correction circuit