SN74AUC2G86DCUR

This dual 2-input exclusive-OR gate is operational at 0.8–V to 2.7–VCC, but is designed specifically for 1.65-V to 1.95-V VCC operation. The SN74AUC2G86 performs the Boolean function Y = A⊕B or Y = ĀB + A B̄ in positive logic. A common application is as a true/complement element. If the input is low, the other input is reproduced in true form at the output. If the input is high, the signal on the other input is reproduced inverted at the output. NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

Applications

• True/complement unit: when one input is LOW, the other input signal passes through to the output in true form; when one input is HIGH, the other input signal appears at the output in complemented form
• Logic identity unit: output is LOW when all inputs are at the same logic level
• Even-parity unit: output is LOW when an even number of inputs (0 or 2) are active
• Odd-parity unit: output is HIGH when an odd number of inputs (only 1 of 2 inputs) are active
• Various XOR logic-related applications

Key features

• Available in the Texas Instruments NanoFree™ Package
• Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
• Ioff Supports Partial-Power-Down Mode Operation
• Sub-1-V Operable
• Max tpd of 1.7 ns at 1.8 V
• Low Power Consumption, 10-μA Max ICC
• ±8-mA Output Drive at 1.8 V
• Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
• ESD Protection Exceeds JESD 22: 2000-V Human-Body Model (A114-A), 200-V Machine Model (A115-A), 1000-V Charged-Device Model (C101)