SN74AUP1T87DCKR

The SN74AUP1T87 performs the Boolean function Y = A(overline) ⊕ B(overline) with designation for logic-level translation applications with output referenced to supply VCC. AUP technology is the lowest-power logic technology for extending battery-life in operating. All input levels accept 1.8-V LVCMOS signals, while operating from either a single 3.3-V or 2.5-V VCC supply. This product also maintains excellent signal integrity. The wide VCC range of 2.3 V to 3.6 V allows the possibility of switching output level to connect to external controllers or processors. Schmitt-trigger inputs (ΔVt = 210 mV between positive and negative input transitions) offer improved noise immunity during switching transitions, useful on analog mixed-mode designs. Schmitt-trigger inputs reject input noise, ensure integrity of output signals, and allow for slow input signal transition. Ioff allows for powered-down conditions (VCC = 0 V) and is important in portable and mobile applications. When VCC = 0 V, signals in the range from 0 V to 3.6 V can be applied to the inputs and outputs of the device. No damage occurs to the device under these conditions. The SN74AUP1T87 is designed with optimized current-drive capability of 4 mA to reduce line reflections, overshoot, and undershoot caused by high-drive outputs.

Applications

• Logic level translation applications
• Portable, mobile low-power devices
• Analog mixed-mode designs
• Interface with external controllers or processors

Key features

• Single-Supply Voltage Translator
• ESD Performance Tested Per JESD 22: 2000-V Human-Body Model (A114-B, Class II), 1000-V Charged-Device Model (C101)
• Schmitt-Trigger Inputs Reject Input Noise and Provide Better Output Signal Integrity
• Ioff Supports Partial Power Down (VCC = 0 V)
• Very Low Static Power Consumption: 0.1 μA
• Very Low Dynamic Power Consumption: 0.9 μA
• Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
• Pb-Free Packages Available: SC-70 (DCK), 2x2.1x0.65 mm (Height 1.1 mm)