SN74LVC1G86MDCKREP

This single 2-input exclusive-OR gate is designed for 1.65-V to 5.5-V CC operation. The SN74LVC1G86 performs the Boolean function Y = A⊕B or Y = A(overline)B + AB(overline) in positive logic. A common application is as a true/complement element. If the input is low, the other input is reproduced in true form at the output. If the input is high, the signal on the other input is reproduced inverted at the output. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

Applications

• True/complement element: when one input is low, the other input passes through non-inverted; when one input is high, the other input is inverted
• Logic identity element: output asserted low when all inputs are at the same logic level
• Even-parity element: output asserted low when an even number of inputs are active
• Odd-parity element: output asserted high when an odd number of inputs are active

Key features

• Controlled Baseline One Assembly/Test Site, One Fabrication Site
• Extended Temperature Performance of -55℃ to 125℃
• Enhanced Diminishing Manufacturing Sources (DMS) Support
• Enhanced Product-Change Notification
• Qualification Pedigree
• Supports 5-V Vcc Operation
• Inputs Accept Voltages to 5.5 V
• Max tpd of 6.7 ns at 3.3 V
• Low Power Consumption, 15- μA Max ICC
• ±24-mA Output Drive at 3.3 V
• Ioff Supports Partial-Power-Down Mode Operation
• Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
• ESD Protection Exceeds JESD 22:
• 2000-V Human-Body Model (A114-A)
• 200-V Machine Model (A115-A)
• 1000-V Charged-Device Model (C101)