SPC5602PEF0MLL6

Up to 64 MHz, single issue, 32-bit CPU core complex (e200z0h) Compliant with Power Architecture embedded category Variable Length Encoding (VLE) Memory organization Up to 256 KB on-chip code flash memory with ECC and erase/program controller Optional: additional 64 (4x16) KB on-chip data flash memory with ECC for EEPROM emulation Up to 20 KB on-chip SRAM with ECC Fail-safe protection Programmable watchdog timer Non-maskable interrupt Fault collection unit Nexus Class 1 interface Interrupts and events 16-channel eDMA controller 16 priority level controller Up to 25 external interrupts PIT implements four 32-bit timers 120 interrupts are routed via INTC General purpose I/Os Individually programmable as input, output or special function 37 on 64 LQFP 64 on 100 LQFP 1 general purpose eTimer unit 6 timers each with up/down capabilities 16-bit resolution, cascadeable counters Quadrature decode with rotation direction flag Double buffer input capture and output compare Communications interfaces Up to 2 LINFlex modules (1x Master/Slave, 1x Master only) Up to 3 DSPI channels with automatic chip select generation (up to 8/4/4 chip selects) 1 FlexCAN interface (2.0B Active) with 32 message buffers 1 safety port based on FlexCAN with 32 message buffers and up to 8 Mbit/s at 64 MHz capability, usable as second CAN when not used as safety port One 10-bit analog-to-digital converter (ADC) Up to 16 input channels (16 ch on 100 LQFP and 12 ch on 64 LQFP) Conversion time <1 μs including sampling time at full precision Programmable Cross Triggering Unit (CTU) 4 analog watchdogs with interrupt capability On-chip CAN/UART bootstrap loader with Boot Assist Module (BAM) 1 FlexPWM unit 8 complementary or independent outputs with ADC synchronization signals Polarity control, reload unit Integrated configurable dead time unit and inverter fault input pins 16-bit resolution Lockable configuration Clock generation 4–40 MHz main oscillator 16 MHz internal RC oscillator Software-controlled FMPLL capable of up to 64 MHz Voltage supply 3.3 V or 5 V supply for I/Os and ADC On-chip single supply voltage regulator with external ballast transistor Operating temperature ranges: -40 to 125 ℃ or -40 to 105 ℃

Key features

• Core maximum operating frequency 64 MHz, single-issue 32-bit CPU core complex e200z0h, compliant with Power Architecture embedded category, supports Variable Length Encoding VLE
• Memory configuration: up to 256 KB on-chip code flash with ECC and integrated erase/program controller; optional additional 64 KB on-chip data flash with ECC for EEPROM emulation; up to 20 KB on-chip SRAM with ECC
• Integrated fail-safe protection: programmable watchdog timer, non-maskable interrupt, fault collection unit, and Nexus Class 1 interface
• Interrupt system: integrated 16-channel eDMA controller, 16-level priority controller, supports up to 25 external interrupts; PIT module includes 4 × 32-bit timers, routing up to 120 interrupts
• GPIO pins individually programmable as input, output, or special function; 64 LQFP package with 37 GPIO, 100 LQFP package with 64 GPIO
• Integrated 1 general-purpose eTimer unit with 6 timers supporting up/down counting, 16-bit resolution, cascadable counters; supports quadrature decoding with rotation direction flag, double-buffered input capture and output compare
• Integrated multiple communication interfaces: up to 2 LINFlex modules, 3 DSPI channels (with automatic chip select generation), 1 FlexCAN 2.0B Active interface with 32 message buffers, 1 FlexCAN-based safety port (usable as second CAN interface, up to 8 Mbit/s at 64 MHz)
• Integrated 1 × 10-bit ADC, up to 16 input channels (16 channels in 100 LQFP, 12 channels in 64 LQFP), conversion time including sampling less than 1 μs at full accuracy, programmable Cross Triggering Unit CTU with 4 analog watchdogs supporting interrupts
• Integrated 1 FlexPWM unit, 8 complementary or independent outputs with ADC sync signal; supports polarity control and reload unit, integrated configurable dead-time unit and inverter fault input pin, 16-bit resolution, configuration lock support
• On-chip CAN/UART bootloader with Boot Assist Module BAM, integrated CRC module and JTAG controller compliant with IEEE 1149.1
• Clock system: supports 4~40 MHz main oscillator, 16 MHz on-chip RC oscillator, software-controlled FMPLL with up to 64 MHz output
• Power supply: IO and ADC support 3.3 V or 5 V supply, on-chip single-supply regulator with external ballast transistor required
• Operating temperature range: –40℃ to 125℃ or –40℃ to 105℃