TMS5701224CPGEQQ1

The TMS570LS1224 device is a high-performance automotive-grade microcontroller family for safety systems. The safety architecture includes dual CPUs in lockstep, CPU and memory BIST logic, ECC on both the flash and the data SRAM, parity on peripheral memories, and loopback capability on peripheral I/Os. The TMS570LS1224 device integrates the ARM Cortex-R4F floating-point CPU which offers an efficient 1.66 DMIPS/MHz, and has configurations which can run up to 180 MHz providing up to 298 DMIPS. The device supports the word-invariant big-endian [BE32] format. The TMS570LS1224 device has 1.25MB of integrated flash and 192KB of data RAM with single-bit error correction and double-bit error detection. The flash memory on this device is a nonvolatile, electrically erasable and programmable memory, implemented with a 64-bit-wide data bus interface. The flash operates on a 3.3-V supply input (same level as I/O supply) for all read, program, and erase operations. When in pipeline mode, the flash operates with a system clock frequency of up to 180 MHz. The SRAM supports single-cycle read and write accesses in byte, halfword, word, and double-word modes throughout the supported frequency range. The TMS570LS1224 device features peripherals for real-time control-based applications, including two Next Generation High-End Timer (N2HET) timing coprocessors with up to 44 I/O terminals, seven Enhanced Pulse Width Modulator (ePWM) modules with up to 14 outputs, six Enhanced Capture (eCAP) modules, two Enhanced Quadrature Encoder Pulse (eQEP) modules, and two 12-bit Analog-to-Digital Converters (ADCs) supporting up to 24 inputs. The N2HET is an advanced intelligent timer that provides sophisticated timing functions for real-time applications. The timer is software-controlled, using a reduced instruction set, with a specialized timer micromachine and an attached I/O port. The N2HET can be used for pulse-width-modulated outputs, capture or compare inputs, or general-purpose I/O (GIO). The N2HET is especially well suited for applications requiring multiple sensor information and drive actuators with complex and accurate time pulses. A High-End Timer Transfer Unit (HTU) can perform DMA-type transactions to transfer N2HET data to or from main memory. A Memory Protection Unit (MPU) is built into the HTU. The ePWM module can generate complex pulse width waveforms with minimal CPU overhead or intervention. The ePWM is easy to use and it supports both high-side and low-side PWM and deadband generation. With integrated trip zone protection and synchronization with the on-chip MibADC, the ePWM module is ideal for digital motor control applications. The eCAP module is essential in systems where the accurately timed capture of external events is important. The eCAP can also be used to monitor the ePWM outputs or for simple PWM generation when the eCAP is not needed for capture applications.

Applications

• Braking Systems (ABS and ESC)
• Electric Power Steering (EPS)
• HEV and EV Inverter Systems
• Battery Management Systems
• Active Driver Assistance Systems
• Railway Communications
• Off-road Vehicles

Key features

• High-Performance Automotive-Grade Microcontroller for Safety-Critical Applications – Dual CPUs Running in Lockstep – ECC on Flash and RAM Interfaces – Built-In Self-Test (BIST) for CPU and On-chip RAMs – Error Signaling Module With Error Pin – Voltage and Clock Monitoring
• ARM Cortex-R4F 32-Bit RISC CPU – 1.66 DMIPS/MHz With 8-Stage Pipeline – FPU With Single- and Double-Precision 12-Region Memory Protection Unit (MPU) – Open Architecture With Third-Party Support
• Operating Conditions – Up to 180-MHz System Clock Core Supply Voltage (VCC): 1.14 to 1.32 V – I/O Supply Voltage (VCCIO): 3.0 to 3.6 V
• Integrated Memory – 1.25MB of Program Flash With ECC – 192KB of RAM With ECC – 64KB of Flash for Emulated EEPROM With ECC
• 16-Bit External Memory Interface (EMIF)
• Common Platform Architecture – Consistent Memory Map Across Family – Real-Time Interrupt (RTI) Timer (OS Timer) – 128-Channel Vectored Interrupt Module (VIM) – 2-Channel Cyclic Redundancy Checker (CRC)
• Direct Memory Access (DMA) Controller – 16 Channels and 32 Control Packets – Parity Protection for Control Packet RAM – DMA Accesses Protected by Dedicated MPU
• Frequency-Modulated Phase-Locked Loop (FMPLL) With Built-In Slip Detector
• Separate Nonmodulating PLL
• IEEE 1149.1 JTAG, Boundary Scan and ARM CoreSight Components
• Advanced JTAG Security Module (AJSM)
• Calibration Capabilities – Parameter Overlay Module (POM)
• 16 General-Purpose Input/Output (GPIO) Pins Capable of Generating Interrupts
• Enhanced Timing Peripherals for Motor Control – 7 Enhanced Pulse Width Modulator (ePWM) Modules – 6 Enhanced Capture (eCAP) Modules – 2 Enhanced Quadrature Encoder Pulse (eQEP) Modules
• Two Next Generation High-End Timer (N2HET) Modules – N2HET1: 32 Programmable Channels – N2HET2: 18 Programmable Channels – 160-Word Instruction RAM Each With Parity Protection – Each N2HET Includes Hardware Angle Generator – Dedicated High-End Timer Transfer Unit (HTU) for Each N2HET
• Two 12-Bit Multibuffered Analog-to-Digital Converter (MibADC) Modules – ADC1: 24 Channels – ADC2: 16 Channels Shared With ADC1 – 64 Result Buffers Each With Parity Protection
• Multiple Communication Interfaces – Three CAN Controllers (DCANs) – 64 Mailboxes Each With Parity Protection – Compliant to CAN Protocol Version 2.0A and 2.0B – Inter-Integrated Circuit (I²C) – Three Multibuffered Serial Peripheral Interface (MibSPI) Modules – 128 Words Each With Parity Protection – 8 Transfer Groups – Up to Two Standard Serial Peripheral Interface (SPI) Modules – Two UART (SCI) Interfaces, One With Local Interconnect Network (LIN 2.1) Interface Support
• Packages – 144-Pin Quad Flatpack (PGE) [Green] – 337-Ball Grid Array (ZWT) [Green]