TMS5704357BZWTQQ1

The TMS570LC4357 device belongs to the high-performance automotive-grade ARM Cortex - R based MCU of the Hercules TMS570 series. This device is equipped with comprehensive documentation, tools, and software to assist in the development of ISO 26262 and IEC 61508 functional safety applications. The TMS570LC4357 device integrates two ARM Cortex - R5F floating-point CPUs operating in lockstep, with an efficiency of up to 1.66 DMIPS/MHz. They can run at a frequency of up to 300MHz, providing a performance of up to 498 DMIPS. The device supports the big-endian [BE32] format. The TMS570LC4357 device has 4MB of integrated flash memory with single-bit error correction and double-bit error detection capabilities and 512KB of data RAM. The flash memory on this device is an electrically erasable and programmable non-volatile memory with a 64-bit wide data bus interface. For all read, programming, and erase operations, the flash operates at a 3.3V power supply input (the same level as the I/O power supply). The SRAM supports read/write access in byte, half-word, and word modes. The TMS570LC4357 device has peripherals for real-time control applications, including two next-generation high-end timer (N2HET) timing coprocessors with a total of up to 64 I/O pins. The device has two 12-bit resolution MibADCs, with a total of 41 channels and a 64-word buffer RAM with parity protection. The device has multiple communication interfaces: 5 MibSPIs; 4 UART (SCI) interfaces, 2 of which support LIN; 4 CANs; 2 I2C modules; 1 Ethernet controller; and 1 FlexRay controller. The frequency modulation phase-locked loop (FMPLL) clock module multiplies an external frequency reference by a higher frequency for internal use. The global clock module (GCM) manages the mapping between available clock sources and internal device clock domains. The device also has two external clock prescaler (ECP) modules. The direct memory access (DMA) controller has 32 channels, 48 peripheral requests, and ECC protection for its memory. The error signaling module (ESM) monitors on-chip device errors and determines whether to trigger an interrupt or an external error pin/bond pad (nERROR) when a fault is detected. The external memory interface (EMIF) provides memory expansion for asynchronous and synchronous memories or other slave devices. The device includes a parameter override module to enhance the debugging function of application code. The device implements several interfaces to enhance the debugging function of application code. With integrated safety features and various communication and control peripherals, the TMS570LC4357 device is well-suited for high-performance real-time control applications with strict safety requirements.

Applications

• Braking systems (ABS and ESC)
• Electric Power Steering (EPS)
• HEV and EV inverter systems
• Battery management systems
• Active driver assistance systems
• Rail transportation
• Off-road vehicles

Key features

• High-performance automotive-grade MCU for safety-critical applications
• Dual-core lockstep CPU with ECC-protected cache
• ECC on flash and RAM interfaces
• Built-in self-test for CPU, high-end timers, and on-chip RAM
• Error Signaling Module (ESM) with error pin
• Voltage and clock monitoring
• ARM Cortex-R5F 32-bit RISC CPU
• Single- and double-precision FPU
• 16-region Memory Protection Unit (MPU)
• 32KB instruction cache and 32KB data cache (ECC-protected)
• Open architecture with third-party support
• CPU clock up to 300MHz
• Core supply voltage (VCC): 1.14V to 1.32V
• I/O supply voltage (VCCIO): 3.0V to 3.6V
• 4MB program flash with ECC support
• 512KB RAM with ECC support
• 128KB data flash (EEPROM emulation) with ECC support
• 16-bit External Memory Interface (EMIF)
• Hercules common platform architecture
• Consistent memory map across the family
• Real-Time Interrupt (RTI) timer (OS timer)
• Two 128-channel Vector Interrupt Modules (VIM) with vector table ECC protection
• VIM1 and VIM2 operating in safety lockstep mode
• Two dual-channel Cyclic Redundancy Checker (CRC) modules
• Direct Memory Access (DMA) controller
• 32 channels and 48 peripheral requests
• ECC protection for control packet RAM
• DMA access protected by dedicated MPU
• Frequency-Modulated Phase-Locked Loop (FMPLL) with built-in missing clock detector
• Independent non-modulated PLL
• IEEE 1149.1 JTAG, boundary scan, and ARM CoreSight components
• Advanced JTAG Security Module (AJSM)
• Trace and calibration features
• ETM, RTP, DMM, POM
• Multiple communication interfaces
• 10/100Mbps Ethernet MAC (EMAC)
• IEEE 802.3 compliant (3.3V I/O only)
• MII, RMII, and MDIO support
• Dual-channel FlexRay controller
• 8KB message RAM with ECC protection
• Dedicated FlexRay Transfer Unit (FTU)
• Four CAN controller (DCAN) modules
• 64 mailboxes with ECC protection
• Compatible with CAN protocol version 2.0B
• Two Inter-Integrated Circuit (I2C) modules
• Five Multi-buffered Serial Peripheral Interface (MibSPI) modules
• MibSPI1: 256 words with ECC protection
• Other MibSPI: 128 words with ECC protection
• Four UART (SCI) interfaces, two with LIN 2.1 support
• Two Next Generation High-End Timer (N2HET) modules
• 32 programmable channels per module
• 256-word instruction RAM with parity protection
• Hardware angle generator per N2HET
• Dedicated High-End Timer Transfer Unit (HTU) per N2HET
• Two 12-bit Multi-buffered ADC (MibADC) modules
• MibADC1: 32 channels + control for up to 1024 off-chip channels
• MibADC2: 25 channels
• 16 shared channels
• 64 result buffers with parity protection
• Enhanced timer peripherals
• Seven Enhanced PWM (ePWM) modules
• Six Enhanced Capture (eCAP) modules
• Two Enhanced Quadrature Encoder Pulse (eQEP) modules
• Three on-chip temperature sensors
• Up to 145 GPIO pins
• 16 dedicated GPIO pins with external interrupt capability
• 337-ball Grid Array (ZWT) package [Green]