PIC24FJ256DA210T-I/PT

Key features

• Three Graphics Hardware Accelerators to Facilitate Rendering of Block Copying, Text and Unpacking of Compressed Data
• Color Look-up Table (CLUT) with Maximum of 256 Entries
• 1/2/4/8/16 bits-per-pixel (bpp) Color Depth Set at Run Time
• Display Resolution Programmable According to Frame Buffer: Supports direct access to external memory on devices with EPMP Resolution supported is up to 480×272@60Hz 16 bpp; 640×480@30 Hz, 16 bpp or 640×480@60 Hz, 8 bpp
• Supports Various Display Interfaces: 4/8/16-bit Monochrome STN, 4/8/16-bit Color STN, 9/12/18/24-bit Color TFT (18 and 24-bit displays are connected as 16-bit, 5-6-5 RGB color format)
• USB 2.0 On-The-Go (OTG) Compliant
• Dual Role Capable - Can act as either Host or Peripheral
• Low-Speed (1.5 Mbps) and Full-Speed (12 Mbps) USB Operation in Host mode
• Full-Speed USB Operation in Device mode
• High-Precision PLL for USB
• Supports up to 32 Endpoints (16 bidirectional): USB module can use the internal RAM location from 0x800 to 0xFFFF as USB endpoint buffers
• On-Chip USB Transceiver with Interface for Off-Chip Transceiver
• Supports Control, Interrupt, Isochronous and Bulk Transfers
• On-Chip Pull-up and Pull-Down Resistors
• Enhanced Parallel Master Port/Parallel Slave Port (EPMP/PSP), 100-pin devices only: Direct access from CPU with an Extended Data Space (EDS) interface, 4, 8 and 16-bit wide data bus, Up to 23 programmable address lines, Up to 2 chip select lines, Up to 2 Acknowledgement lines (one per chip select), Programmable address/data multiplexing