PIC24FJ64GA006-I/PT

This series is a 16-bit microcontroller with a rich peripheral feature set and enhanced computational performance. The PIC24FJ128GA010 series also provides a new migration path, primarily targeting applications that require a platform beyond 8-bit but do not need a DSP.

Key features

• High-Performance CPU:
• Enhanced Harvard architecture
• Up to 16 MIPS @ 32 MHz operating performance
• 8 MHz internal oscillator with 4x PLL option and multiple divider options
• 17-bit x 17-bit single-cycle hardware multiplier
• 32-bit/16-bit hardware divider
• 16-bit x 16-bit working register array
• Optimized C compiler instruction set architecture: 76 base instructions with flexible addressing modes
• Two address generation units for independent read and write addressing of data memory
• MCU Special Features:
• Operating voltage range: 2.0V to 3.6V
• Flash program memory: 1000 erase/write cycles endurance, minimum 20-year data retention
• Self-reprogrammable under software control
• Optional power management modes: Sleep, Idle, and Alternate Clock modes
• Fail-Safe Clock Monitor operation: switches clock source to on-chip low-power RC oscillator upon detection of clock failure
• On-chip 2.5V voltage regulator
• JTAG boundary scan and programming support
• Power-on Reset (POR), Power-up Timer (PWRT), and Oscillator Start-up Timer (OST)
• Flexible programmable Watchdog Timer (WDT) with on-chip low-power RC oscillator for reliable device operation
• In-Circuit Serial Programming™ (ICSP™) and In-Circuit Emulation (ICE) via 2 pins
• Analog Features:
• 10-bit ADC with up to 16 channels, 500 ksps conversion rate, conversion capability in Sleep and Idle modes
• 2 analog comparators with programmable input/output configuration
• Peripheral Features:
• Two 3-wire/4-wire SPI modules supporting 4 frame modes with 8-level FIFO buffer
• Two I²C™ modules supporting multi-master/slave mode and 7-bit/10-bit addressing
• Two UART modules: RS-232, RS-485, and LIN 1.2 support; on-chip hardware encoder/decoder with IrDA capability; auto-wake-up on Start bit; auto-baud rate detection; 4-level FIFO buffer
• Parallel Master/Slave Port (PMP/PSP): 8-bit or 16-bit data, 16 address lines
• Hardware Real-Time Clock/Calendar (RTCC): clock, calendar, and alarm functions
• Programmable Cyclic Redundancy Check (CRC): user-programmable polynomial, 8/16-level FIFO buffer
• Five 16-bit timer/counters with programmable prescaler
• Five 16-bit capture inputs
• Five 16-bit compare/PWM outputs
• High sink/source current on all I/O pins: 18 mA
• Digital I/O pins configurable as open-drain outputs
• Up to 5 external interrupt sources
• 5.5V-tolerant inputs (digital inputs only)
• Core Features:
• 16-bit Architecture:
• 16-bit data path and 24-bit address path for data space and memory space transfers
• Linear addressing up to 8 MB (program) and 64 KB (data)
• 16×16 working register array with software stack support
• 17-bit x 17-bit hardware multiplier for integer operations
• Hardware support for 32-bit/16-bit division
• Instruction set with multiple addressing modes, optimized for high-level languages such as C
• Up to 16 MIPS operating performance
• Power-Saving Technologies:
• Dynamic Clock Switching: device clock switchable under software control to Timer1 clock source or internal low-power RC oscillator during operation, enabling power-saving design in software
• Doze Mode: reduces CPU clock speed for time-critical applications (e.g., serial communication) requiring continuous peripheral operation, enabling further power savings without data loss
• Instruction-Based Power-Saving Modes: a single software instruction can halt all operations or shut down only the core while keeping peripherals active
• Oscillator Options and Performance:
• 2 crystal modes using crystal or ceramic resonator
• Two external clock modes with divide-by-2 clock output option
• One Fast Internal Oscillator (FRC) with nominal output of 8 MHz, software-divisible down to 31 kHz
• One Phase Lock Loop (PLL) multiplier, available in external oscillator mode and FRC oscillator mode